Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry

ABSTRACT

Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods offorming devices on or over a substrate, forming device arrays on or overa substrate, forming conductive lines on or over a substrate, andforming capacitor arrays on or over a substrate. The invention alsorelates to semiconductor device arrays, and in particular to series ofconductive lines and capacitor arrays.

BACKGROUND OF THE INVENTION

[0002] Circuit devices which are fabricated on or over semiconductorwafers typically undergo one or more photolithographic steps duringformation. During such photolithographic steps, device features can beetched using conventional techniques. The spacing between such devicesis important because often times adjacent devices must be electricallyisolated from one another to avoid undesirable shorting conditions.

[0003] One of the limitations on device spacing stems from limitationsinherent in the photolithographic process itself. In the prior art,devices are generally spaced only as close as the photolithographiclimit will permit.

[0004] By way of example and referring to FIGS. 1 and 2, a semiconductorwafer fragment is indicated generally by reference numeral 25. Fragment25 includes a substrate 29 atop which a material 28 is provided. Aplurality of patterned masking layers 26 are formed atop material 28.

[0005] Referring to FIG. 3, material 28 is anisotropically etched toform lines 30 atop substrate 29. As shown, individual lines haverespective widths L₁ which constitute the minimum photolithographicfeature size available for a line. Typically, a separation S₁ separatesadjacent lines across the substrate as shown. Such dimension istypically only slightly larger than L₁ but could be the same as L₁. Theterm “pitch” as used in this document is intended to be in itsconventional usage, and is defined as the distance between one edge of adevice and the corresponding same edge of the next adjacent device.Accordingly and in the illustrated example, the pitch between adjacentlines P1 (i.e., from the left illustrated edge of one line to the leftillustrated edge of the next immediately adjacent line) is equal to thesum of L₁ and S₁,

[0006] As integrated circuitry gets smaller and denser, the need toreduce spacing dimensions or pitch, such as S₁ and P₁. becomesincreasingly important. This invention grew out of the need to reducethe size of integrated circuits, and particularly the need to reducespacing dimensions and pitches between adjacent devices over asemiconductor wafer.

SUMMARY OF THE INVENTION

[0007] The invention includes semiconductor processing methods andrelated integrated circuitry in which a plurality of patterned deviceoutlines are formed over a semiconductor substrate. Electricallyinsulative partitions or spacers are then formed on at least a portionof the patterned device outlines, after which a plurality ofsubstantially identically shaped devices are formed relative to thepatterned device outlines. Individual formed devices are spaced from atleast one other of the devices by a distance substantially no more thana width of one of the electrically insulative spacers.

[0008] According to one aspect of the invention, elongated electricallyconductive lines are formed. According to another aspect of theinvention, capacitors are formed. In one preferred implementation of thelatter aspect, a pair of adjacent capacitor containers are formed over asubstrate by etching a first capacitor container opening having at leastone sidewall. An electrically insulative spacer is formed over thesidewall. A second capacitor container opening is etched selectivelyrelative to the spacer. Capacitors are then formed in the capacitorcontainers in a manner such that adjacent capacitors have a separationdistance which is substantially no greater than the width of the spacerbetween the adjacent capacitors.

[0009] A novel masking layout is provided which allows capacitors to beformed in a manner which reduces device pitch by almost 50%. Such isparticularly adaptive for use in fabrication of DRAM circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0011]FIG. 1 is a top plan view of a prior art semiconductor waferfragment atop which a plurality of masking layers are formed, and isdiscussed in the “Background” section above.

[0012]FIG. 2 is a side sectional view of the FIG. 1 prior artsemiconductor wafer taken along line 2-2 in FIG. 1.

[0013]FIG. 3 is a view of the FIG. 1 prior art semiconductor waferfragment at a processing step subsequent to that shown in FIG. 1.

[0014]FIG. 4 is a top plan view of a semiconductor wafer fragment atopwhich a plurality of masking layers are formed at one processing step inaccordance with one aspect of the invention.

[0015]FIG. 5 is a side view of the FIG. 4 semiconductor wafer fragment.

[0016]FIG. 6 is a view of the FIG. 5 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 5.

[0017]FIG. 7 is a view of the FIG. 5 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 6.

[0018]FIG. 8 is a view of the FIG. 5 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 7.

[0019]FIG. 9 is a view of the FIG. 5 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 8.

[0020]FIG. 10 is a top plan view of the FIG. 9 semiconductor waferfragment.

[0021]FIG. 11 is a view of a semiconductor wafer fragment at oneprocessing step in accordance with another aspect of the invention.

[0022]FIG. 12 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 11.

[0023]FIG. 13 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 12.

[0024]FIG. 14 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 13.

[0025]FIG. 15 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 14.

[0026]FIG. 16 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 15.

[0027]FIG. 17 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 16.

[0028]FIG. 18 is a view of the FIG. 11 semiconductor wafer fragment at aprocessing step subsequent to that shown by FIG. 17.

[0029]FIG. 19 is a top plan view of a portion of a semiconductor masklayout in accordance with one aspect of the invention.

[0030]FIG. 20 is a top plan view of the FIG. 19 semiconductor masklayout with a portion highlighted for purposes of discussion.

[0031]FIG. 21 is a view of a portion of the FIG. 20 semiconductor masklayout highlighted portion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Referring initially to FIGS. 4 and 5, a plurality of patterneddevice outlines 32 are photolithographically formed over asemiconductive substrate 34. In the context of this document, the term“semiconductive substrate” is defined to mean any constructioncomprising semiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove. In this illustrated and preferred example, the materialconstituting outlines 32 is preferably of the type which can be etchedselectively relative to substrate 34. Such outlines define areas oversubstrate 34 in which conductive lines are to be formed. Such patterneddevice outlines are, dimension-wise, substantially the same as those setforth with regard to patterned masking layers 26 in FIGS. 1-3.

[0033] Referring to FIG. 6, an electrically insulative material such asSiO₂ or Si₃N₄ is formed over lines 32 and substrate 34 and subsequentlyanisotropically etched to provide a plurality of sidewall spacers 36 onat least a portion, and preferably all, of pattern device outlines 32.For purposes of the ongoing discussion, patterned device outlines 32define male patterns between which female patterns 38 are also formed.Accordingly, an array of alternating male/female patterns are formedover the substrate wherein sidewall spacers 36 are formed in femalepatterns 38.

[0034] Referring to FIG. 7, and after forming sidewall spacers 36, malepatterns or patterned device outlines 32 are removed as by suitableetching techniques. The etch preferably etches device outlines 32relative to the material forming spacers 36 and the substrate 34. Suchleaves behind a plurality of upstanding sidewall spacers 36 whicheffectively define thin electrically insulative partitions between whicha plurality of devices are to be formed. As shown, the distance orlateral spacing between adjacent spacers varies from spacer-to-spacer.According to one preferred aspect, a plurality of spaces 40 a through 40i are provided wherein adjacent spaces, such as 40 a and 40 b differslightly in lateral width dimension, while alternate spaces such as 40 aand 40 c have as shown substantially the same lateral width dimension.

[0035] Referring to FIG. 8, a conductive material 42 is formed oversubstrate 34 and sidewall spacers 36 and preferably completely fillsspaces 40 a through 40 i. An example material for layer 32 isconductively doped polysilicon.

[0036] Referring to FIG. 9, conductive material 42 is etched back as bysuitable methods such as a chemical-mechanical polish (CMP) or dryetching as well known in the art. Such forms a plurality ofsubstantially identically shaped circuit devices relative to thepatterned device outlines 32 (FIG. 6). In this embodiment, such devicesare conductive lines 44 which are spaced laterally from one another adistance which is no greater than a width of one of the electricallyinsulative sidewall spacers 36 therebetween. As so formed, immediatelyadjacent conductive lines of the plurality of lines formed have a pitchP₂ which is substantially no greater than a lateral line width L₂ plus awidth W₂ of the spacer 36 which is positioned between the adjacentlines. As compared to the pitch P₁ (FIG. 3) of the prior , circuitdevices, pitch P2 represents a reduction in pitch which approaches fiftypercent. Such achieved pitch reductions are without regard to the priorart photolithographic spacing constraints imposed on semiconductorprocessing. As mentioned above, the spacing between adjacent spacersvaries from spacer-to-spacer. Accordingly, the pitch P₂ would vary aswell. It is possible for the spacing between adjacent spacers to beuniform, however, so that the pitch remains constant across thesubstrate.

[0037] Referring to FIG. 10, a top plan view of substrate 34 is shown.Conductive lines 44 collectively define a series of conductive lineswhich in turn define a device array 46 of substantially identicallyshaped devices. Array 46 includes the plurality of upstanding spacers 36and the conductive lines 44 formed intermediate the spacers. Inaccordance with a preferred aspect of the invention and as describedwith reference to FIG. 9 above, adjacent lines have a pitch which issubstantially no greater than about the distance between a pair ofadjacent spacers (corresponding to the line width) plus the width of thespacer therebetween. In the illustrated example, conductive lines 44 areelongated and adjacent conductive lines have different lateral linewidths. Additionally, alternate lines have substantially equal lateralline widths. Such variation in line width stems from the manner in whichthe anisotropically etched sidewall spacers 36 are provided over thesubstrate, and in particular the lateral spacing of device outlines 32(FIG. 5). As mentioned above, it is possible for the line widths to besubstantially equal over the entire substrate.

[0038] Referring still to FIG. 10, a dashed line 48 traverses devicearray 46. Individual elongated conductive lines 44 are formed oversubstrate 34 transversely along line 48. Respective alternate devicesalong line 48 have a substantially common width dimension therealong andrespective adjacent devices have a different width dimension therealong.

[0039] Referring collectively to FIGS. 11-18, a semiconductor processingmethod of forming a plurality of alternate devices on a substrate inaccordance with the above-described principles is described. Accordingto a preferred aspect of the invention, the devices comprise capacitors,and even more preferably comprise capacitors which form part of adynamic random access memory (DRAM) device. Circuit devices other thanthe illustrated and described conductive lines and capacitors can befabricated in accordance with the invention.

[0040] In accordance with one preferred embodiment, a plurality ofcapacitor container openings are etched over a substrate in two separateetching steps. Thereafter, corresponding DRAM capacitors are formedwithin the container openings according to known processing techniques.As so formed, and in accordance with the above-described spacerformation and pitch reduction concepts, a plurality of pairs of adjacentcapacitors are formed in respective adjacent capacitor containers whichare separated by no more than anisotropically etched, electricallyinsulative sidewall spacers as will become evident below.

[0041] Referring specifically to FIG. 11, a semiconductor wafer fragmentin process is shown generally at 50 and includes a layer of material 52which may or not may be semiconductive. Transistors forming part of thepreferred DRAM circuitry array are not shown, but are formed preferablyelevationally below the capacitors described hereafter. Otherelevational configurations as between transistors and capacitors arepossible. A layer 54, preferably of borophosphosilicate glass (BPSG), isformed over material 52 to a thickness preferably around two microns. Alayer of photoresist material 58 formed over the substrate and patternedto define a plurality of bit line contact openings 56 over waferfragment 50. The illustrated and preferred photoresist material 58defines a plurality of patterned device outlines 60 over the substrate.Patterned outlines 60 in turn define individual areas over the substratefor supporting a plurality of capacitors to be formed as describedbelow. Preferably, the individual areas defined by outlines 60 supporttwo such capacitors as will be apparent.

[0042] Referring to FIG. 12, layer 54 is anisotropically etched to formbit line contact openings 62 into layer 54. Photoresist material 58 isthen stripped and an insulating material is formed over the substrateand into openings 62 and subsequently anisotropically etched to form theillustrated sidewall spacers 64. Thereafter, bit contact material,preferably conductively doped polysilicon, is formed over the substrateand into openings 62. Such material is or may be planarized as bysuitable chemical-mechanical polishing to provide the illustrated bitline contacts or plugs 66. A plurality of contacts similar to contacts66 are formed over the substrate during the same formation steps andbound each area 60 across the substrate in the same manner as theillustrated contacts 66 bound the centermost area 60.

[0043] Referring to FIG. 13, a first set of capacitor container openingpatterns 68 are formed over the substrate and defined by photoresistmaterial 69. The device pattern set forth in FIG. 13 results from asemiconductor mask layout which is shown in FIG. 19 and discussed indetail below. FIG. 13 is a view which is taken along line 13-13 in FIG.19.

[0044] Referring to FIG. 14, a first set 70 of capacitor containeropenings are etched selectively relative to spacers 64 and theconductive contacts 66 through layer 54. Photoresist material 69 is thenstripped away. Individual capacitor containers 72 of first set 70 haveat least one, and preferably more, upright sidewalls, two of which areillustrated at 74, 76 respectively for each container 72. Uprightsidewalls 74 as viewed in FIG. 14 coincide with and are defined by therightmost sidewall spacer 64 which was previously formed.

[0045] Referring to FIG. 15, an electrically insulative material such assilicon nitride is formed over the substrate and subsequentlyanisotropically etched relative to layer 54, spacers 64, and bit linecontacts 66 to form respective partitions or spacers 78, 80. Individualareas defined by outlines 60 are thus partitioned into two parts whichare separated from one another by non-conducting partitions 78, 80,respectively, which are formed over and cover sidewalls 74, 76respectively. As so formed, partitions 78, 80 outline individualcontainer openings of first set 70 in which capacitors are to be formed.

[0046] Referring to FIG. 16, remaining BPSG layer 54 is selectivelyetched or otherwise removed relative to sidewall spacers 64, spacers orpartitions 78, 80, and bit line contacts 66 to define a second set 82 ofcapacitor container openings to respective capacitor containers 84. Asso etched, individual second set containers 84 and the respectiveopenings thereof are disposed adjacent respective first set containers72 to form a pair of containers (only one complete pair 72/84 of whichis shown). The leftmost side of FIG. 16 shows a leftmost outline 60which includes a complete capacitor container 84 and a portion of itspaired container 72. Likewise, the rightmost side of FIG. 16 shows arightmost outline 60 which includes a complete capacitor container 72and a portion of its paired container 84. Individual containers of apair are separated therefrom by no more than the width of anon-conducting partition 80. As discussed above with reference to thepitch advantages achieved with conductive lines 44 (FIGS. 9 and 10),such advantages are achieved through the use of spacers or partitions 80which electrically isolate adjacent capacitors formed in respectiveareas 60.

[0047] Referring to FIGS. 17 and 18, electrically conductive containermaterial 86 is formed over the substrate and planarized (FIG. 18) todefine a plurality of capacitor storage nodes 81 in preferred containershapes. Subsequently, capacitors are formed according to conventionalformation techniques as by provision of a dielectric layer 83 overrespective storage nodes 81 and provision of a subsequent polysiliconlayer 85 thereover. As so formed, capacitors in respective partitionedparts of the area defined by outlines 60 are separated from immediatelyadjacent capacitors or have a closest separation distance which issubstantially no greater than the width of the partition or spacerbetween the capacitors.

[0048] Referring to FIG. 19, a diagrammatic semiconductor mask layoutand DRAM array is designated generally by reference numeral 88. Layout88 is utilized to enable the above-described container openings to beselectively, alternately formed or etched in the two described separateetching steps. For purposes of clarity, FIG. 13 is taken along line13-13 in FIG. 19 at a processing point just after the patterning ofphotoresist material 69 (FIG. 13) with layout 88. Layout 88 enablescapacitors having unique, space-saving geometries to be formed over thesubstrate. According to a preferred aspect of the invention, theelectrically insulative partitions 78, 80 (FIG. 16) are formed betweenadjacent capacitors intermediate the two etching steps which form ordefine the areas over the substrate in which the capacitors will beformed. The partitions 78, 80 are not shown for clarity in FIG. 19.

[0049] Mask layout 88 includes a plurality of rows such as thoseillustrated at R₁, R₂, R₃, and R₄. The mask layout also includes aplurality of columns such as those illustrated at C₁, C₂, C₃, C₄, C₅,C₆, and C₇. A plurality of masked areas 90 and a plurality of adjacentunmasked areas 92 are defined by the layout. Unmasked areas 92correspond to capacitor container opening patterns 68 in FIG. 13 andmasked areas 90 correspond to photoresist material 69. Layout 88 enablesa plurality of capacitors to be formed, preferably as part of a DRAMarray over the substrate, wherein respective alternate capacitors in arow, such as rows R₁-R₄ have substantially similar lateral widthprofiles transverse the row. Preferably, respective adjacent capacitorsin a row have different lateral width profiles transverse the row. Theillustrated and preferred lateral width profiles when viewed from apoint above the substrate approximate triangles which are oriented in atop-to-bottom fashion across the row. Additionally, individual definedareas in which the preferred capacitor pairs are to be formed(corresponding to the view taken along line 13-13 in column C₅)approximate a diamond shape with such shape having at its respectivecorners, bit line contacts 94 which are formed as described above. Forpurposes of the ongoing discussion, each of columns C₁l-C₇ are formedalong a generally straight line which is generally transverse each ofrows R₁-R₄. Further, the array of capacitor pairs to be formed areformed along individual lines which contain at least one of the pairs ofcapacitors. As such, the array is defined by a plurality of the lines(corresponding to the plurality of the columns) which contain aplurality of capacitors which are separated by substantially no morethan an electrically insulative anisotropically etched spacer asdescribed above. Underlying word lines are shown by dashed lines 93 andinterconnect associated transistors formed relative to the substrate.Individual bit lines are not specifically shown but are subsequentlyformed and oriented generally transversely relative to word lines 93.

[0050] Referring to FIG. 20, mask layout 88 defines in part a DRAM arraywhich includes a plurality of six-capacitor geometries which are to beformed over the substrate. A representative of one of the geometries isindicated generally by reference numeral 96 and a plurality of adjacentor other geometries are shown in phantom lines. The illustrated andpreferred six-capacitor geometries are, in turn, defined by a pluralityof individual polygonal capacitor geometries shown collectively at 98through 108. Preferably, collective individual capacitor geometries 98through 108 approximate a hexagon individual sides of which are definedby a side of a different respective one of the individual polygonalcapacitor geometries. For example, six-capacitor geometry or hexagon 96includes six sides collectively shown at 96 a, 96 b, 96 c, 96 d, 96 e,and 96 f. Each of such sides is defined by a different respective one ofthe individual sides of the individual polygonal capacitor geometries 98through 108. According to a preferred aspect of the invention,individual polygonal capacitor geometries 98 through 108, when viewedoutwardly of the substrate approximate a wedge or wedge-shape. Even morepreferably, such individual geometries approximate a triangle which,most preferably, is an isosceles triangle. Further, individualapproximated isosceles triangles include equal adjacent angles 0 whichapproximate a range of between about 50° to 70°. Such equal adjacentangles are shown for individual geometries 100, 104, and 108. Even morepreferably, such equal adjacent angles approximate an angle of about65°. Individual geometries 98 through 102 and 104 through 108respectively, are preferably arranged in a top-to-bottom orientationsuch that hexagon 96 can be bisected, as by dashed line 110, into halveswhich contain 14 exactly three individual polygonal capacitorgeometries. In the illustrated and preferred hexagon, one of the halves,a top half as viewed in FIG. 20 contains individual geometries 98, 100,and 102. The other of the halves, a bottom half, contains geometries104, 106, and 108.

[0051] Referring to FIG. 21, the top half containing geometries 98, 100,and 102 is shown. Such comprises a three-capacitor geometry 112, aplurality of which are disposed over the substrate. Preferably,three-capacitor geometry 112, when viewed outwardly of the substratedefines a pair of overlapping approximated parallelograms, theintersection of which approximates a triangle. The first of suchparallelograms is shown at 114. The second of such parallelograms isshown at 116. Parallelogram 114 includes sides 114 a, 114 b, 114 c, and114d. Parallelogram 116 includes sides 116 a, 116 b, 116 c, and 116 d.The parallelograms share sides 114 b and 116 d. As shown, eachapproximated parallelogram is bounded at a respective one of its cornersby a bit line contact 94. The approximated triangle defined by theintersection of parallelograms 114, 116 includes sides 114 c, 116 c andshared sides 114 b/ 116 d. For purposes of ongoing discussion, aplurality of capacitor pairs are selectively and alternately etched overthe substrate along etch axes which are generally orthogonal relative tothe substrate and into the plane of the page upon which FIG. 21 appears.Such capacitor pairs can approximate the above described parallelogramand would include the individual capacitors etched as a result ofindividual geometries 98, 100, or alternatively 100, 102.

[0052] Referring to both FIGS. 16 and 19, a DRAM array is formed atop asubstrate and includes a first set of capacitors formed in first setcapacitor openings 70 over the substrate. A second set of capacitors areformed over the substrate and in second set capacitor openings 82.Individual capacitors of the first set are bounded by at least threecapacitors from the second set (FIG. 19). Preferably, individual firstset capacitors have a closest separation distance from at least one ofthe three bounding capacitors which is substantially no more than awidth of an electrically insulative anisotropically etched spacer. Onesuch width is indicated in FIG. 16 at 80. Even more preferably,individual bounded first set capacitors have closest separationdistances from no less than two and preferably three of the boundingcapacitors which are no more than the width of an electricallyinsulative anisotropically etched spacer formed or provided between therespective capacitors.

[0053] The above described semiconductor device forming methods andintegrated circuitry formed thereby constitute an improvement whichrelates to device spacing over a substrate. Such improvement enablesdevice pitch to be reduced by almost fifty percent or more whichrepresents a substantial space savings over heretofore available methodsand devices.

[0054] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming integrated circuit devices comprising: forming aplurality of patterned device outlines over a semiconductive substrate;forming electrically insulative spacers on at least a portion of thepatterned device outlines; and forming a plurality of substantiallyidentically shaped devices relative to the patterned device outlines, atleast two individual devices of the plurality being spaced from oneanother by a distance no greater than a width of an interposedelectrically insulative spacer.
 2. The method of forming integratedcircuit devices of claim 1, wherein the devices are elongatedelectrically conductive lines.
 3. The method of forming integratedcircuit devices of claim 1, wherein the devices include capacitors of aDRAM array.
 4. The method of forming integrated circuit devices of claim1, wherein the plurality of devices are formed along a line, respectivealternate devices along the line having a substantially common widthdimension.
 5. The method of forming integrated circuit devices of claim1, wherein the plurality of devices are formed along a line, respectiveadjacent devices along the line having different width dimensions. 6.The method of forming integrated circuit devices of claim 1, wherein thedevices include capacitors of a DRAM array, the capacitors being formedin rows, respective alternate capacitors in a row having substantiallysimilar width profiles transverse the row.
 7. The method of formingintegrated circuit devices of claim 1, wherein the devices includecapacitors of a DRAM array, the capacitors being formed in rows,adjacent capacitors in a row having different width profiles transversethe row.
 8. The method of forming integrated circuit devices of claim 1,wherein the devices include capacitors of a DRAM array, the capacitorsbeing formed in rows, respective alternate capacitors in a row havingsubstantially similar width profiles transverse the row, adjacentcapacitors in the row having different width profiles transverse therow.
 9. A method of forming a plurality of integrated circuitry deviceson a substrate comprising: forming a plurality of spaced, upstanding,anisotropically etched electrically insulative spacers; and forming aplurality of devices over the substrate intermediate the spacers withthe spacers being positioned intermediate adjacent devices, adjacentdevices having a pitch which is substantially no greater than about thedistance between a pair of adjacent spacers plus the width of the spacerbetween the adjacent devices.
 10. The method of forming a plurality ofintegrated circuitry devices of claim 9, wherein the devices areconductive lines.
 11. The method of forming a plurality of integratedcircuitry devices of claim 9, wherein the devices are capacitors. 12.The method of forming a plurality of integrated circuitry devices ofclaim 9, wherein the devices are capacitors of a DRAM device.
 13. A DRAMcapacitor forming method comprising the steps of: forming a plurality ofpatterned outlines over a semiconductive substrate to define individualareas for a plurality of capacitors to be formed; partitioning saidindividual areas from one another by a nonconducting partition; andforming capacitors in at least some of the respective partitioned areas,the respective capacitors being separated from immediately adjacentcapacitors by a distance substantially no greater than the width of thepartition therebetween.
 14. The DRAM capacitor forming method of claim13, wherein the partitioning step comprises: etching a first set ofcapacitor container openings, individual container openings having atleast one upright sidewall; and etching a second set of capacitorcontainer openings adjacent respective first set container openings andseparated therefrom by respective non-conducting partitions.
 15. TheDRAM capacitor forming method of claim 13, wherein the partitioning stepcomprises: etching a first set of capacitor container openings,individual container openings having at least one upright sidewall;forming insulative material over the substrate; anisotropically etchingthe insulative material to provide partitions over at least some of theupright sidewalls; and etching a second set of capacitor containeropenings immediately adjacent the provided partitions.
 16. The DRAMcapacitor forming method of claim 13 wherein individual defined areas.when viewed from a point above the substrate, approximate diamondshapes.
 17. A DRAM capacitor forming method comprising the steps of:forming a pair of adjacent capacitor containers over a substrate byetching a first capacitor container opening having at least one uprightsidewall; forming an electrically insulative spacer on the uprightsidewall; selectively etching a second capacitor container openingadjacent the formed spacer; forming capacitors in the capacitorcontainers, adjacent capacitors having a separation distancetherebetween which is substantially no greater than the width of thespacer between the adjacent capacitors.
 18. The DRAM capacitor formingmethod of claim 17, wherein the step of forming the electricallyinsulative spacer comprises: forming an insulative material over thesubstrate; and anisotropically etching the insulative material to formthe spacer.
 19. The DRAM capacitor forming method of claim 17, whereinindividual capacitor containers are generally triangularly shaped whenviewed from a point above the substrate.
 20. A method of formingcapacitors comprising forming an array of capacitor pairs on asubstrate, the array being defined in part by a plurality of lines,individual lines containing at least one pair of capacitors, individualcapacitors of said at least one pair of capacitors being separated bysubstantially no more than an electrically insulative anisotropicallyetched spacer disposed therebetween.
 21. The method of formingcapacitors of claim 20 further comprising prior to forming the array ofcapacitor pairs, forming a plurality of bit line contacts in individuallines, individual capacitor pairs being bounded by at least two bit linecontacts.
 22. The method of forming capacitors of claim 20 whereinindividual capacitor pairs have a pitch no greater than about a lateralwidth dimension of one of the capacitors plus the width of theanisotropically etched spacer between the capacitors of an individualpair.
 23. A DRAM capacitor array comprising: a substrate; a first set ofcapacitors over the substrate; and a second set of capacitors over thesubstrate, individual capacitors of the first set being bounded by atleast three capacitors from the second set, individual first setcapacitors having a closest separation distance from at least one of thethree capacitors from the second set which is substantially no more thana width of an interposed electrically insulative anisotropically etchedspacer.
 24. The DRAM capacitor array of claim 23, wherein individualbounded first set capacitors have closest separation distances from noless than two of the three capacitors from the second set, said closestseparation distances being substantially no more than a width of aninterposed electrically insulative anisotropically etched spacer. 25.The DRAM capacitor array of claim
 23. wherein individual bounded firsrset capacitors have closest separation distances from the threecapacitors from the second set which are substantially no more than awidth of an interposed electrically insulative anisotropically etchedspacer.
 26. A method of forming a plurality of capacitors in asemiconductor memory device comprising the steps of: selectivelyremoving substrate material to define a first set of containers; formingsidewall spacers adjacent container sidewalls; selectively removingremaining substrate material adjacent the spacers to define a second setof containers; and forming capacitors in the containers separated onlyby the spacers.
 27. The method of forming a plurality of capacitors ofclaim 26 further comprising prior to defining the first set ofcontainers: forming a plurality of bit line contact openings over thesubstrate, individual bit line contact openings having at least onesidewall; and covering the at least one sidewall of the plurality of bitline contact openings with an insulating material.
 28. The method offorming a plurality of capacitors of claim 26 further comprising priorto defining the first set of containers: forming a plurality of bit linecontact openings over the substrate, individual bit line contactopenings having at least one sidewall; covering the at least onesidewall of the plurality of bit line contact openings with aninsulating material; etching the insulating material to form sidewallspacers; and forming electrically conductive material in the bit linecontact openings to provide bit line contacts, wherein the defining ofthe first set of containers includes selectively etching the first setof containers relative to the sidewall spacers and the electricallyconductive material of the bit line contacts.
 29. A DRAM capacitorforming method comprising forming a plurality of pairs of adjacentcapacitors in respective adjacent capacitor containers separated bysubstantially no more than anisotropically etched sidewall spacers. 30.The DRAM capacitor forming method of claim 29, wherein individual pairsof adjacent capacitors, when viewed from a point over the substrate areapproximately diamond shaped.
 31. The DRAM capacitor forming method ofclaim 29 further comprising forming a plurality of bit line contactopenings over the substrate prior to forming the capacitor pairs. 32.The DRAM capacitor forming method of claim 29 further comprising forminga plurality of bit line contact openings over the substrate prior toforming the capacitor pairs, and wherein individual pairs of adjacentcapacitors, when viewed from a point over the substrate areapproximately diamond shaped, individual bit line contact openings beingpositioned in respective corners of the diamonds.
 33. A capacitor arrayfor a DRAM comprising: a plurality of bit line contacts to a substrate;and a plurality of capacitor pairs selectively alternately etched over asubstrate along etch axes which are generally orthogonal relative to thesubstrate, individual capacitor pairs having an area which, when viewedfrom outwardly of the substrate from a point on such etch axes,approximates a parallelogram which is bounded at a plurality of itscorners by individual bit line contacts.
 34. A processing method offorming a capacitor array for a DRAM comprising: forming a plurality ofbit line contacts to a substrate; and forming a plurality of capacitorpairs, individual pairs being selectively alternately etched over asubstrate and along etch axes which are generally orthogonal relative tothe substrate, individual capacitor pairs having an area which, whenviewed from outwardly of the substrate from a point on such etch axes,approximates a parallelogram which is bounded at a plurality of itscorners by individual bit line contacts.
 35. A method of forming aplurality of DRAM capacitors comprising: etching capacitor containeropenings for an array in a substrate in at least two separate etchingsteps, and forming electrically insulative partitions between adjacentcapacitors intermediate the two etching steps.
 36. The method of claim35 wherein the forming electrically insulative partitions stepcomprises: forming insulative material over the substrate; andconducting an anisotropic etch of the insulative material to a degreesufficient to leave the partitions.
 37. A processing method of forming aplurality of DRAM capacitors comprising etching capacitor containeropenings for a capacitor array in a substrate in two separate etchingsteps.
 38. A DRAM capacitor array comprising: a plurality of 6-capacitorgeometries over a substrate, individual 6-capacitor geometries beingdefined by a plurality of individual generally polygonal capacitorgeometries, and further, individual 6-capacitor geometries, when viewedfrom above the substrate, approximating a hexagon, each individual sideof which being defined by a side of a different respective one of theindividual polygonal capacitor geometries.
 39. The DRAM capacitor arrayof claim 38, wherein individual polygonal capacitor geometries, whenviewed from above the substrate approximate a wedge shape.
 40. The DRAMcapacitor array of claim 38, wherein individual polygonal capacitorgeometries, when viewed from above the substrate approximate a triangle.41. The DRAM capacitor array of claim 38, wherein individual polygonalcapacitor geometries, when viewed from above the substrate approximatean isosceles triangle.
 42. The DRAM capacitor array of claim 38, whereinindividual polygonal capacitor geometries, when viewed from above thesubstrate approximate an isosceles triangle equal adjacent angles ofwhich approximate a range of between about 500 to 70°.
 43. The DRAMcapacitor array of claim 38, wherein individual polygonal capacitorgeometries, when viewed from above the substrate approximate anisosceles triangle equal adjacent angles of which approximate about 65°.44. The DRAM capacitor array of claim 38, wherein the hexagon can bebisected into halves containing exactly three individual polygonalcapacitor geometries.
 45. A DRAM capacitor array comprising: a pluralityof 3-capacitor geometries over a substrate, individual 3-capacitorgeometries, when viewed from above the substrate being defined by a pairof overlapping approximated parallelograms, the intersection of whichapproximates a triangle.
 46. A method of forming adjacent devices over asubstrate comprising: lithographically forming an array of patterneddevice outlines over a substrate, the outlines defining alternatingmale/female patterns; forming electrically insulative sidewall spacersin the female patterns; after forming the electrically insulativesidewall spacers, removing the male patterns; and after removing themale patterns, forming circuit devices adjacent the spacers.
 47. Anintegrated device array of substantially identically shaped devicescomprising: a plurality of spaced upstanding anisotropically etchedelectrically insulative spacers; and a plurality of devices formed overthe substrate intermediate the spacers with the spacers being positionedintermediate adjacent devices, adjacent devices having a pitch which issubstantially no greater than about the distance between a pair ofadjacent spacers plus the width of the spacer between the adjacentdevices.
 48. The integrated device array of claim 47, wherein thedevices are conductive lines.
 49. The integrated device array of claim47, wherein the devices are capacitors.
 50. The integrated device arrayof claim 47, wherein the devices are capacitors and the device arrayforms part of a DRAM device.